Multiple data state memory cell

ABSTRACT

A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.

TECHNICAL FIELD

[0001] The invention relates to random access memories (“RAMs”), andmore particularly to memory cells of a RAM capable of storing data inmultiple data states.

BACKGROUND OF THE INVENTION

[0002] Random access memory devices are an integral part of anycomputing environment. Without these memory devices, processing data ina computing device would be nearly impossible. Consequently, there hasbeen a great amount of research and development directed to the area ofrandom access computer memory. The research and development has beendirected to different areas related to computer memory, for example, inincreasing the speed at which data stored by the memory devices can beaccessed, in designing memories with lower power consumption, and inengineering memory devices having greater data retention times.Additionally, one particular area to which a great amount of effort hasbeen spent is in the areas of increasing memory density and datacapacity.

[0003] One conventional approach to increasing memory density has beento decrease the size of memory devices, and more particularly, decreasethe size of memory cells. As a result, the size of memory cells havebeen reduced dramatically in the recent past. However, the size ofmemory cells have diminished to the point where the current state ofprocessing technology is being constantly challenged when manufacturingmemory devices with these feature sizes. Another approach to the memorydensity and data capacity issue has been experiment with memory devicesthat are capable of storing data in more states than conventional binarymemory. That is, conventional memory stores data in a binary format,where data is stored as either one of two different data states. Withmultiple data state memory, data can be stored as one of many differentstates, where the number of different states is greater than two. As aresult, with multiple data state memory, generally less memory cellsneed to be used to store data. For example, a memory cell having fourdifferent data states can be substituted for two conventional memorycells having only two different data states. Consequently, only half asmany memory cells would be needed to store the same quantity of data.Conversely, twice as much data can be stored in the same area if themultiple data state memory is the same size as conventional memorycells.

[0004] An example of the type of work that has been done in the area ofmultiple data state memory is provided in several U.S. patents toOvshinsky et al. For example, in U.S. Pat. No. 5,296,716 to Ovshinsky etal., the use of electrically writeable and erasable phase changematerials for electronic memory applications is described. Additionally,in U.S. Pat. No. 5,912,839 to Ovshinsky et al., a method of programmingOvonic memory multistate-digital multibit memory elements and the use indata storage is described. As described therein, a memory elementincluding the phase change material, that is, materials which can beelectrically switched between generally amorphous and generallycrystalline, can be programmed by using a number of current pulses. Indetermining the data state of the memory element, the number of pulsescan be discerned by counting the number of pulses required to return theresistance level of the memory element to a first state. The number ofpulses represents the data state of the data stored by the memoryelement. As further described in the aforementioned patent, the processof reading the present state of the memory element is destructive, andconsequently, requires that the data is reprogrammed following a read.

[0005] Another approach that has been taken in the design of multipledata state memory is described in U.S. patents to Kozicki et al. Asdescribed therein, a programmable metallization cell (PMC) formed from afast ion conductor, such as a chalcogenide material that includecompounds containing sulfur, selenium and tellurium, positioned betweentwo electrodes. The formation of a non-volatile metal dendrite can beinduced by application of a voltage difference between the twoelectrodes. The mass of the non-volatile dendrite changes the resistanceof the PMC, which can be used as a means to store data in variousstates. Further described in the aforementioned patents are variousstructural embodiments of a PMC in different applications.

[0006] Although there has been development in the area of multiple datastate and variable resistance memories, it will be appreciated that newand alternative approaches to this area is still possible. For example,further development in the area of multiple data state memory cellshaving true quantization of data states. Therefore, there is a need foralternative approaches to storing data in multiple data states.

SUMMARY OF THE INVENTION

[0007] The present invention is directed to a multiple data state memorycell. The memory cell includes a first electrode layer formed from afirst conductive material, a second electrode layer formed from a secondconductive material, and a first layer of a metal-doped chalcogenidematerial disposed between the first and second electrode layers, thefirst layer providing a medium in which a conductive growth can beformed to electrically couple together the first and second electrodelayers. The memory cell further includes a third electrode layer formedfrom a third conductive material, and a second layer of a metal-dopedchalcogenide material disposed between the second and third electrodelayers, the second layer providing a medium in which a conductive growthcan be formed to electrically couple together the second and thirdelectrode layers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a cross-sectional view of an embodiment of theinvention.

[0009]FIGS. 2a-c are cross-sectional views of the embodiment of FIG. 1illustrating the operation thereof.

[0010]FIG. 3 is a cross-sectional view of another embodiment of theinvention.

[0011]FIG. 4 is a block diagram of a typical memory device that includesone or more memory arrays of the present embodiment.

[0012] As is conventional in the field of integrated circuitrepresentation, the lateral sizes and thicknesses of the various layersare not drawn to scale and may have been enlarged or reduced to improvedrawing legibility.

DETAILED DESCRIPTION OF THE INVENTION

[0013] Embodiments of the present invention provide a multiple statememory cell. Certain details are set forth below to provide a sufficientunderstanding of the invention. However, it will be clear to one skilledin the art that the invention may be practiced without these particulardetails. In other instances, well-known fabrication techniquesprocessing methods, circuits, control signals, and timing protocols havenot been shown in detail in order to avoid unnecessarily obscuring theinvention.

[0014] Illustrated in FIG. 1 is a cross-sectional view of a portion of amultiple-state memory cell 200 according to an embodiment of the presentinvention. A metal electrode layer 202 is formed to provide a cathodelayer to which a voltage is applied. It will be appreciated that themetal layer 200 may be formed on a substrate, or on a layer of materialwhich will support the multiple-state memory cell 200. Formed on themetal layer 200 is a metal-doped chalcogenide layer 204 through which,as will be explained in more detail below, a conductive link to floatingelectrode layer 206 is formed under the application of a voltage.Chalcogenide materials, as referred to herein, include those compoundsof sulfur, selenium, and tellurium. The metal material doping thechalcogenide are generally Group I or Group II metals, such as silver,copper, zinc, and combinations thereof. The floating electrode layer 206is typically formed from a metal material, such as silver.

[0015] Formed on the floating electrode layer 206 is a anothermetal-doped chalcogenide layer 208. The composition of the material forlayer 208 may be, but does not necessarily need to be, the same as thelayer 204. As illustrated in FIG. 2, the thickness t₂ of the layer 208is greater than the thickness t₁ of the layer 204. However, in otherembodiments of the present invention, the thicknesses t₂ and t₁ may benearly or approximately the same, or the thickness t₂ may be less thant₁. As will be explained in more detail below, the composition of therespective metal-doped chalcogenide layers 206 and 208 may need to bemodified in order to accommodate layers 206 and 208 having variousthicknesses. Formed on the metal-doped chalcogenide layer 208 is anothermetal electrode layer 210, which represents an anode of themultiple-state memory cell 200. The metal electrode layer 210 and thefloating electrode layer 206 are typically formed from the samematerial. As illustrated in FIG. 1, the cathode is formed below theanode, however, it will be appreciated that the arrangement of the twolayers may be reversed as well without departing from the scope of thepresent invention. Moreover, the vertical orientation illustrated inFIG. 1 can be changed such that the various layers are formed in ahorizontal orientation between a cathode and an anode that are laterallyspaced apart from one another.

[0016] It will be appreciated that many materials known by those ofordinary skill in the art may be used for the metal-doped chalcogenidelayers. For example, compositions of germanium selenide, Ge_(x)Se_(y),can be used. Exemplary ratios are in the range from Ge₂₀Se₈₀ to GeSe.Compositions of arsenic sulfide, germanium telluride, and germaniumsulfide can also be used for the metal-doped chalcogenide layers.Similarly, materials that can be used for the electrode layers are alsoknown, such as silver, compositions of silver selenide, copper,germanium selenide, and the like. It will be appreciated that laterdeveloped materials that display the same characteristics as knownmaterials can also be used for the metal-doped chalcogenide andelectrode layers without deviating from the scope of the presentinvention.

[0017] In operation, the multiple-state memory cell 200 illustrated inFIG. 1 is capable of storing multiple states by altering or programmingthe total resistance between the anode and the cathode in a relativelydigital fashion. The resistance of the memory cell 200 can then measuredor compared to determine the value of the data stored by the memory cell200. As a result of the relatively discrete manner in which theresistance can be changed, multiple states can be stored by the memorycell 200.

[0018] The alteration of the resistance is accomplished by the formationof a conductive growth from the metal electrode layer 202 (i.e., thecathode) through the layer 204 to electrically contact the floatingelectrode layer 206, and the formation of a conductive growth from thefloating electrode layer 206 through the layer 208 to electricallycontact the metal electrode layer 210 (i.e., the anode). The formationof the conductive growth is induced by creating a voltage differencebetween the cathode and the anode, such as by applying a voltage to theanode and grounding the cathode.

[0019] Each time a conductive growth creates a short circuit, theresistance between the anode and the cathode changes relativelysignificantly. Initially, as shown in FIG. 2a, where no conductivegrowth has been formed, the resistance between the anode and the cathodeR_(cell) is equal to approximately R₁+R₂, where R₁ is the resistance ofthe layer 204 and R₂ is the resistance of the layer 208. However, underthe influence of an applied bias across the metal-doped chalcogenidelayers 202, 210, conductive growths 304 and 308 begin to form throughthe layers 204 and 208, respectively. When the conductive growth 308extends through the layer 208 and creates a short circuit between thethe floating electrode layer 206 and the anode, which is represented bythe layer 210, as shown in FIG. 2b, the resistance R_(cell) between theanode and the cathode changes to a value less than R₁ but greater than ashort circuit. The resistance R_(cell) at this point is reproducible,and consequently, can be used to represent a data state. The resistanceR_(cell) changes again, as shown in FIG. 2c, to a relatively lowresistance when a conductive growth 304 extends through the layer 204and creates a short circuit between the cathode, which is represented bythe layer 202, and the floating electrode layer 206.

[0020] Each of the different resistance states of R_(cell) provided bythe memory cell 200 represents a different data or logic state. That is,a first data state is represented by R_(cell) being approximately equalto the total resistance (R1+R2), a second data state is represented byR_(cell) being a value between R₁ and low resistance, which occurs whenthe floating electrode layer 206 is short circuited to the metalelectrode layer 210 by the conductive growth 308, and a third data stateis represented by a low resistance after the metal electrode layer 202is short circuited to the floating electrode layer 206 by the conductivegrowth 304. A reading circuit coupled to the memory cell 200 measuresthe resistance of the memory cell 200 in order to determine the datastored by the cell.

[0021] The growth of the conductive growths 304 and 308 is dependent onthe orientation of the electrical field applied to the memory cell 200.That is, as discussed so far, a voltage applied to the metal electrodelayer 210 (i.e., the anode) is positive relative to the voltage appliedto the metal electrode layer 202 (i.e., the cathode), thus, thedirection of growth is from the metal electrode layer 202 to thefloating electrode layer 206. Similarly, a conductive growth will beformed extending from the floating electrode layer 206 to the metalelectrode layer 210. However, it will be appreciated that application ofthe voltage in an opposite polarity will reduce whatever conductivegrowth has been previously formed. Consequently, the memory cell 200 canbe programmed to store a different data state by changing the polarityof the applied voltage to the memory cell 200 during a read or writeoperation to change the resistance of the memory cell 200.

[0022] It will be further appreciated that reading and writing circuitryfor use with embodiments of the present invention is well known to thoseof ordinary skill in the art, and may be implemented using conventionalcircuitry and design. It will be further appreciated that thedescription provided herein is sufficient to enable one of ordinaryskill in the art to practice the invention.

[0023] As illustrated in FIG. 2b, application of a voltage to the anodeinduces the formation of not only conductive growth 304, but conductivegrowth 308 as well. However, because the thickness of the layer 208 isgreater than the thickness of the layer 204, for a given applied voltageacross the multiple state memory cell 200 the voltage across the layer208 is greater than the voltage across the layer 204. Consequently, thefloating electrode 206 is short circuited to the anode before thecathode is short circuited to the floating electrode 206. With continuedapplication of a voltage to the anode, the conductive growth 304eventually creates a short circuit between the cathode and the floatingelectrode 206, thus reducing the resistance between the anode and thecathode to a low resistance. Moreover, it will be appreciated that theresistance R_(cell) across the anode and cathode is between R₁ and ashort circuit after the conductive growth 308 short circuits thefloating electrode 206 to the anode 210 because the resistance of thelayer 204 is actually reduced as the conductive growth 304 grows towardthe floating electrode 206. However, the resistance R_(cell) at thispoint is nevertheless reproducible and different enough from the shortcircuited state that conventional reading circuits for multiple-statememory cells can consistently recognize the data state.

[0024] It will be further appreciated that the range of resistances, orthe transition from one resistance relative to one another can beadjusted by altering the thickness of the layers 204 and/or 208.Additionally, as previously mentioned, the composition of themetal-doped chalcogenide material of the layers 204 and 208 can beadjusted as well to adjust the points of transition in the resistance.

[0025] Illustrated in FIG. 3 is a portion of a memory cell 400 accordingto another embodiment of the present invention. The memory cell 400includes layers that are similar to those of the memory cell 200 (FIG.1). However, memory cell 400 further includes a second floatingelectrode 420 and a third metal-doped chalcogenide layer 424 in additionto the layers described with respect to the memory cell 200. Theaddition of the second floating electrode 420 and the third metal-dopedchalcogenide layer 424 enables the memory cell 400 to have an additionalmemory state in which to store data. That is, whereas the memory cell200 provides three different states or resistances R_(cell): (R₂+R₁),between R₁ and low resistance, and low resistance, the memory cell 400provides four different states or resistances for R_(cell): (R₃+R₂+R₁),between (R₂+R₁) and R₁, between R₁ and low resistance, and lowresistance. As previously discussed, each different resistance level canbe used to represent a different state of data.

[0026] As illustrated by the previous discussion, it will be appreciatedthat including additional layers formed from a metal-doped chalcogenidematerial and a floating electrode can be used to create memory cellshaving even more states than that provided by the memory cell 400.

[0027] A memory device 500 that includes a memory array 502 havingmemory cells according to an embodiment of the invention is shown inFIG. 4. The memory device 500 includes a command decoder 506 thatreceives memory command through a command bus 508 and generatescorresponding control signals. A row or column address is applied to thememory device 500 through an address bus 520 and is decoded by a rowaddress decoder 524 or a column address decoder 528, respectively.Memory array read/write circuitry 530 are coupled to the array 502 toprovide read data to a data output buffer 534 via a input-output databus 540. Write data are applied to the memory array through a data inputbuffer 544 and the memory array read/write circuitry 530.

[0028] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A multiple-state memory cell, comprising: a first electrode layerformed from a first conductive material; a second electrode layer formedfrom a second conductive material; a first layer of a metal-dopedchalcogenide material disposed between the first and second electrodelayers, the first layer providing a medium in which a conductive growthcan be formed to electrically couple together the first and secondelectrode layers; a third electrode layer formed from a third conductivematerial; and a second layer of a metal-doped chalcogenide materialdisposed between the second and third electrode layers, the second layerproviding a medium in which a conductive growth can be formed toelectrically couple together the second and third electrode layers. 2.The memory cell of claim 1 wherein the first conductive materialcomprises a composition of a silver material.
 3. The memory cell ofclaim 1 wherein at least one of the first or second layers ofmetal-doped chalcogenide material is a material selected from the groupconsisting of germanium selenide, arsenic sulfide, germanium telluride,and germanium sulfide.
 4. The memory cell of claim 1 wherein thematerial of at least one of the first or second layers of metal-dopedchalcogenide material comprises a composition of germanium selenide. 5.The memory cell of claim 1 wherein the conductive material of the first,second and third electrodes is the same.
 6. The memory cell of claim 1wherein the thickness of the first layer of a metal-doped chalcogenidematerial is less than the thickness of the second layer of a metal-dopedchalcogenide material.
 7. The memory cell of claim 1 wherein thethickness of the second layer of a metal-doped chalcogenide material isless than the thickness of the first layer of a metal-doped chalcogenidematerial.
 8. The memory cell of claim 1, further comprising: a fourthelectrode formed from a fourth conductive material; and a third layer ofa metal-doped chalcogenide material disposed between the third andfourth electrode layers, the third layer providing a medium in which aconductive growth can be formed to electrically couple together thethird and fourth electrodes.
 9. The memory cell of claim 1 wherein themetal-doped chalcogenide material of the first and second layers are thesame.
 10. The memory cell of claim 1 wherein the metal-dopedchalcogenide material of the first and second layers comprise a silverglass material.
 11. A multiple-state memory cell, comprising: a firstelectrode coupled to a first voltage; a second electrode coupled to asecond voltage; a multiple layer data state stack in which multiple datastates are stored, the data-state stack including: a first portion of ametal-doped chalcogenide material adjoining the first electrode, thefirst portion having a first thickness; a third electrode of aconductive material adjoining the first portion; and a second portion ofa metal-doped chalcogenide material adjoining the third electrode, thesecond portion having a second thickness, wherein application of aprogramming voltage to the first electrode induces the formation of afirst conductive growth from the third electrode to the first electrodeand a second conductive growth from the second electrode to the thirdelectrode.
 12. The memory cell of claim 11 wherein the first voltage ispositive relative to the second voltage.
 13. The memory cell of claim 11wherein the first voltage is negative relative to the second voltage.14. The memory cell of claim 11 wherein the first portion is positionedbelow the third electrode, and the third electrode is positioned belowthe second portion.
 15. The memory cell of claim 11 wherein the firstportion is positioned laterally adjacent to the third electrode, and thethird electrode is positioned laterally adjacent to the second portion.16. The memory cell of claim 11 wherein the first thickness is less thanthe second thickness.
 17. The memory cell of claim 11 wherein under theapplication of the programming voltage, the first conductive growthcouples the third electrode to the first electrode prior to the secondconductive growth coupling the second electrode to the third electrode.18. A multiple state memory cell, comprising: a first electrode layerformed from a first conductive material; a second electrode layer formedfrom a second conductive material; a first layer of a metal-dopedchalcogenide material disposed between and adjoining the first andsecond electrode layers, the first layer providing a medium in which aconductive growth can be formed to electrically couple together thefirst and second electrode layers; a third electrode layer formed from athird conductive material; a second layer of a metal-doped chalcogenidematerial disposed between and adjoining the second and third electrodelayers, the second layer providing a medium in which a conductive growthcan be formed to electrically couple together the second and thirdelectrode layers; a fourth electrode layer formed from a fourthconductive material; and a third layer of a metal-doped chalcogenidematerial disposed between and adjoining the third and fourth electrodelayers, the third layer providing a medium in which a conductive growthcan be formed to electrically couple together the third and fourthelectrode layers.
 19. The memory cell of claim 18 wherein at least oneof the first, second, third, and fourth electrode layers comprises acomposition of a silver material.
 20. The memory cell of claim 18wherein the first, second, third, and fourth conductive material are thesame.
 21. The memory cell of claim 18 wherein the thickness of the firstlayer of a metal-doped chalcogenide material is less than the thicknessof the second layer of a metal-doped chalcogenide material, and thethickness of the second layer of a metal-doped chalcogenide material isless than the thickness of the third layer of a metal-doped chalcogenidematerial.
 22. The memory cell of claim 18 wherein the metal-dopedchalcogenide material of the first, second, and third layers are thesame.
 23. The memory cell of claim 18 wherein the metal-dopedchalcogenide material of at least one of the first, second, or thirdlayers comprises a material selected from the group consisting ofgermanium selenide, arsenic sulfide, germanium telluride, and germaniumsulfide.
 24. The memory cell of claim 18 wherein the metal-dopedchalcogenide material of at least one of the first, second, or thirdlayers comprises a composition of germanium selenide.
 25. The memorycell of claim 18 wherein the first electrode is positioned below thesecond electrode, the second electrode is positioned below the thirdelectrode, and the third electrode is positioned below the fourthelectrode.
 26. The memory cell of claim 18 wherein under the applicationof the programming voltage, the first conductive growth couples thethird electrode to the first electrode prior to the second conductivegrowth coupling the second electrode to the third electrode.
 27. Amemory device, comprising: a memory array comprising a plurality ofmemory cells arranged in rows and columns, each memory cell comprising:a first electrode layer formed from a first conductive material andcoupled to a respective row; a second electrode layer formed from asecond conductive material; a first layer of a metal-doped chalcogenidematerial disposed between and adjoining the first and second electrodelayers, the first layer providing a medium in which a conductive growthcan be formed to electrically couple together the first and secondelectrode layers; a third electrode layer formed from a third conductivematerial and coupled to a respective column; and a second layer of ametal-doped chalcogenide material disposed between and adjoining thesecond and third electrode layers, the second layer providing a mediumin which a conductive growth can be formed to electrically coupletogether the second and third electrode layers; a row address decoderfor selecting a row of memory cells corresponding to a row address; acolumn address decoder for selecting a column of memory cellscorresponding to a column address; reading and writing circuitry coupledto the memory array to read data from and write data to the memory cellsselected by the row and column address decoders; a data path coupledbetween the reading and writing circuitry and an external data terminalof the memory device; and a command decoder operable to generate controlsignals responsive to memory commands applied to the memory device. 28.The memory device of claim 27 wherein the first conductive layer of eachmemory cell is formed from a composition of a silver material.
 29. Thememory device of claim 27 wherein the conductive material of the first,second and third electrodes is the same.
 30. The memory device of claim27 wherein the thickness of the first layer of a metal-dopedchalcogenide material is less than the thickness of the second layer ofa metal-doped chalcogenide material.
 31. The memory device of claim 27wherein each memory cell further comprises: a fourth electrode formedfrom a fourth conductive material; and a third layer of a metal-dopedchalcogenide material disposed between the third and fourth electrodelayers, the third layer providing a medium in which a conductive growthcan be formed to electrically couple together the third and fourthelectrodes.
 32. The memory device of claim 27 wherein the metal-dopedchalcogenide material of the first and second layers are the same. 33.The memory device of claim 27 wherein the metal-doped chalcogenidematerial of the first and second layers comprise a silver glassmaterial.
 34. The memory device of claim 27 wherein the metal-dopedchalcogenide material of at least one of the first or second layerscomprises a material selected from the group consisting of germaniumselenide, arsenic sulfide, germanium telluride, and germanium sulfide.35. The memory cell of claim 27 wherein the metal-doped chalcogenidematerial of at least one of the first or second layers comprises acomposition of germanium selenide.
 36. A memory device, comprising: amemory array comprising a plurality of memory cells arranged in rows andcolumns, the memory cells comprising: a first electrode coupled arespective row; a second electrode coupled to a respective column; amultiple layer data state stack in which multiple data states arestored, the data-state stack including: a first layer of a metal-dopedchalcogenide material adjoining the first electrode, the first layerhaving a first thickness; a third electrode layer of a conductivematerial adjoining the first layer; and a second layer of a metal-dopedchalcogenide material adjoining the third electrode layer, the secondlayer having a second thickness, wherein application of a programmingvoltage to the first electrode induces the formation of a firstconductive growth from the third electrode layer to the first electrodeand a second conductive growth from the second electrode too the thirdelectrode layer; a row address decoder for selecting a row of memorycells corresponding to a row address; a column address decoder forselecting a column of memory cells corresponding to a column address;reading and writing circuitry coupled to the memory array to read datafrom and write data to the memory cells selected by the row and columnaddress decoders; a data path coupled between the reading and writingcircuitry and an external data terminal of the memory device; and acommand decoder operable to generate control signals responsive tomemory commands applied to the memory device.
 37. The memory device ofclaim 36 wherein the first voltage is positive relative to the secondvoltage.
 38. The memory device of claim 36 wherein the first portion ispositioned below the third electrode, and the third electrode ispositioned below the second portion.
 39. The memory device of claim 36wherein the first portion is positioned laterally adjacent to the thirdelectrode, and the third electrode is positioned laterally adjacent tothe second portion.
 40. The memory device of claim 36 wherein the firstthickness is less than the second thickness.
 41. The memory device ofclaim 36 wherein under the application of the programming voltage, thefirst conductive growth couples the third electrode to the firstelectrode prior to the second conductive growth coupling the secondelectrode to the third electrode.
 42. A method of storing multiple datastates in a memory, comprising: to store a first data state, shortcircuiting a first electrode to a second electrode to change aresistance from an initial resistance to a first resistance; to store asecond data state, short circuiting the second electrode to a thirdelectrode to change the first resistance to a second resistance; and tostore a third data state, substantially maintaining the initialresistance between the first and second electrodes and the second andthird electrodes.
 43. The method of claim 42 wherein short circuitingthe first electrode to a second electrode comprises applying aprogramming voltage to induce the formation of a conductive growth fromthe first electrode that couples the first electrode to the secondelectrode and wherein short circuiting the second electrode to the thirdelectrode comprises applying the programming voltage to induce theformation of a conductive growth from the second electrode that couplesthe second electrode to the third electrode.
 44. The method of claim 43wherein under the application of the programming voltage the firstelectrode is short circuited to the second electrode prior to the secondelectrode short circuiting to the third electrode.
 45. The method ofclaim 42, further comprising to store a fourth data state, shortcircuiting the third electrode to a fourth electrode to change thesecond resistance to a third resistance.
 46. A method for forming amultiple state memory cell, comprising: forming a first electrode layerfrom a first conductive material; forming a first layer from ametal-doped chalcogenide material on the first electrode layer, forminga second electrode layer from a second conductive material on the firstlayer; forming a second layer from a metal-doped chalcogenide materialon the second electrode layer; and forming a third electrode layer froma third conductive material on the second layer, the first layerproviding a medium in which a conductive growth can be formed toelectrically couple together the first and second electrode layers andthe second layer providing a medium in which a conductive growth can beformed to electrically couple together the second and third electrodelayers.
 47. The method of claim 46 wherein forming the first electrodelayer comprises forming the first electrode layer from a composition ofa silver material.
 48. The method of claim 46 wherein forming the firstand second electrode layers comprises forming the first and secondelectrodes from the same type of material.
 49. The method of claim 46wherein forming the first layer and forming the second layer comprisesforming the first layer having a thickness less than the thickness ofthe second layer.
 50. The method of claim 46 wherein forming the firstlayer and forming the second layer comprises forming the first layerhaving a thickness greater than the thickness of the second layer. 51.The method of claim 46, further comprising: forming a third layer of ametal-doped chalcogenide material on the third electrode layer; andforming a fourth electrode formed from a fourth conductive material onthe third layer, the third layer providing a medium in which aconductive growth can be formed to electrically couple together thethird and fourth electrode layers.
 52. The method of claim 46 whereinthe metal-doped chalcogenide material of the first and second layers arethe same.
 53. The method of claim 46 wherein the metal-dopedchalcogenide material of at least one of the first or second layerscomprises a material selected from the group consisting of germaniumselenide, arsenic sulfide, germanium telluride, and germanium sulfide.54. The memory cell of claim 46 wherein the metal-doped chalcogenidematerial of at least one of the first or second layers comprises acomposition of germanium selenide.
 55. The method of claim 46 whereinthe first electrode is formed beneath the first layer, the first layeris formed beneath the second electrode, the second electrode is formedbeneath the second layer, and the second layer is formed beneath thethird electrode layer.
 56. The method of claim 46 wherein the firstelectrode is formed adjacent the first layer, the first layer is formedadjacent the second electrode, the second electrode is formed adjacentthe second layer, and the second layer is formed adjacent the thirdelectrode layer.